Mar 13 2009, EDN
Now that the USB 3.0 specification is out, we are starting to see public indications of CMOS designers contemplating the requirements. If you haven't been following along, USB 3.0 is a hybrid of sorts: a version of USB that uses essentially PCI Express gen2 signaling to achieve up to 5 Gbit/s raw data rates over media compatible with the connectors and cables of USB 2.0.
And therein lie the issues for chip designers, according to two vendors with whom we've spoken lately, mixed-signal IP vendor Snowbush IP and chip vendor SMSC. Makers of USB 3.0 silicon will be caught between the jaws of a rather nasty vice. On one hand, everyone assumes that anything with a USB label on it will be inexpensive—meaning minimal silicon real estate in a commodity process—and very low in power. On the other hand, employing PCI Express gen2 signaling over a USB-type cable is a very non-trivial undertaking.
Two different kinds of companies are targeting the USB 3.0 market, according to SMSC vice president of engineering Mike Pennell: companies with PCI-Express technology looking to broaden their market, and companies with USB experience seeking to stay in the game. Each brings its own expertise to the problem, and each will have its own challenges to work out.
Snowbush, with a portfolio of existing PCI-Express IP, fits in the former category. For that company, according to Snowbush general manager Ewald Liess, moving to USB 3.0 was a natural product line extension. The company has announced a full-duplex 5 Gbit PHY block based on their PCI-Express technology but compatible with the USB 3.0 spec. "The PHY spec is almost exactly PCI-Express gen2, even down to a modified version of the Pipe interface to the MAC," according to Snowbush director of sales Gary Ruggles.
The company is bringing some new ideas to this market, mainly aimed at trying to meet the low-cost/low-power issues head-on. One example is that rather than using silicon area for a tank-based local oscillator, the company has worked out a self-calibrating ring-oscillator VCO with an internal voltage reference. This design should deal with the considerable process variations customers will see at 65 and 45 nm, according to Ruggles.
Pennell, who gave an invited paper at ISSCC this year on the challenges of USB 3.0, emphasized not so much the similarities to PCI-Express gen2 signaling, but the differences in the physical media. He points out that because 3.0 is supposed to look and feel to users like a much faster version of USB, it will have an entirely different media environment than PCI-Express. Where the latter drives a few centimeters of circuit-board trace, a carefully-designed connector and a daughter card, USB's worst-case scenario will be up to 12 inches of board-trace, a connector pair, a short cable, a front-panel connector and cable connector pair, up to three meters of cable, and another connector pair. A USB 3.0 hub has to handle everything from that mess to a memory stick plugged directly into a connector on the circuit-board —a huge range of physical media.
To deal with this challenge, the standard calls for a fixed transmit pre-emphasis, and an adaptive receive equalizer with a long training sequence. It is not clear just how thoroughly the standards committee explored physical experiments to verify that the specified configuration could actually deal with all the legal configurations that might come up in the field. No doubt there was some lab work. But Pennell comments, based on his experience with the USB 2.0 standard, that a standards committee even with a good lab never anticipates everything that users can throw at you.
Given that uncertainty, Pennell is expecting that USB 3.0 silicon vendors will have to differentiate based on their chips' ability to deal with difficult media configurations. That will mean powerful adaptive equalizers and lots of intelligence in interpreting the training sequences. Unfortunately, the more capable you make your equalizer, other things being equal, the more power and area it consumes. So there could be room for some innovation there. In addition, according to Snowbush's literature, that company has implemented programmable transmitter pre-emphasis, which appears to go beyond the standard's requirements. So it's pretty clear that vendors are taking the media challenge seriously.
A downside here is that after the initial period in which USB 3.0 will sell at premium prices, some vendors may take the low-cost route at the expense of good signaling. That could result in end-users getting bad experiences with 3.0 hardware just as systems vendors are trying to popularize the interface. Think Bluetooth, for instance.
Another point Pennell makes is that there is a voltage problem. The USB 3.0 standard requires legacy support for USB 2.0. Most vendors will approach this with a separate piece of silicon, or at least a separate IP block, since 2.0 PHYs are pretty commodity now. But there is another challenge hidden in the legacy requirement. USB 2.0 uses 3.3V signaling—a voltage level that is not easy to achieve in a 65 or 45 nm process. Worse, there is the matter of the 5V power supply pin that must be present in the USB 2.0 interface. Because that wire is in the cable, both the 2.0 and 3.0 standards presently require that all the signals on the interface, including the high-speed 3.0 signaling pins, tolerate a dead short to +5V. That is probably going to require not only thick oxide, but custom transistor design in the pad ring of 65 nm and 45 nm chips.
So USB 3.0 is coming. There will be both off-the-shelf silicon and licensable IP available well in advance of the first deployments. But there should be a very interesting first couple of years as vendors work out just where to make the tradeoffs between die cost, robust signaling, and electrical durability.
